1. Field of the Invention
The present invention relates to multiplier circuits for analog to digital converters (ADCs). More particularly, the present invention relates to implementations for multiplier circuits to perform gain compensation multiplications and other multiplications required by an ADC during each convolution and to reduce latency in ADC performance.
2. Description of Related Art
Multiplication of two binary numbers, such as an M.times.N bit multiplication, is an inherent part of analog to digital converters (ADCs). Some ADCs require a multiplication during each system clock cycle, whereas others require multiplication only once per conversion to gain up or down the digital word at the end of each convolution of the filter. The latency of an ADC, which refers to the delay time it takes for an ADC to receive an input and provide a converted output, is dependent upon the multiplications required by the ADC and the implementation chosen to accomplish these multiplications.
In general terms, a multiplication may be achieved in an integrated circuit by performing a sequence of add and shift operations. Numerous implementations have been developed for performing a multiplication, such as parallel, partially parallel, serial/parallel, and serial architecture implementations.
In fully parallel architectures, all partial products for the multiplication are formed first, and then added to give the desired result. Partially parallel architectures form some of the partial products and then combine them to give the desired result. Depending on the system clock frequency and the size of the operands, parallel architectures can be made fast so that the multiplication is completed in one system clock cycle. Thus, by using parallel multipliers to perform required multiplications, ADCs have obtained decreased latency and increased throughput. Parallel and partially parallel multipliers, however, make poor use of silicon area, because at any point in time most of the adders in the multiplier are idle.
With an M.times.N bit multiplication using serial/parallel architecture and serial architecture multipliers, the number of cycles required to complete multiplications typically increases resulting in a corresponding increased latency in the performance of ADCs. However, the silicon area required for implementation of these architectures typically decreases, depending upon the particular design. Fully serial multipliers take M.times.N cycles to complete a multiplication, but have the best use of silicon area. Serial/parallel multiplier implementations require M+N cycles using carry-save adders, and require M+1 or N+1 cycles using carry propagate adders. Depending on the multiplier implementation utilized, therefore, it may take 1, N+1, M+1, M+N, or M.times.N cycles to complete a required multiplication.
Serial architectures for ADC multipliers, therefore, provide the best use of silicon area but create the highest latency in the ADC performance, while parallel architectures create the lowest latency in ADC performance but have the worst use of silicon area. In addition, for ADCs that require only a single multiplication operation per convolution, such as a single gain compensation multiplication, parallel and partially parallel multipliers are impractical because of the severe cost in silicon area required for these implementations, and serial multipliers are impractical because they create too much latency in ADC performance.